Alignment between lithography layers is essential for device fabrication. A minor defect in a single marker can lead to incorrect alignment and this can be the source of wafer reworks. In this paper we show that this can be prevented by using extra alignment markers to check the alignment during patterning, rather than inspecting vernier patterns after the exposure is completed. Accurate vernier patterns can often only be read after pattern transfer has been carried out. We also show that by using a Penrose tile as a marker it is possible to locate the marker to about 1 nm without fully exposing the resist. This means that the marker can be reused with full accuracy, thus improving the layer to layer alignment accuracy. Lithography tool noise limits the process.
Thoms, S., Macintyre, D. S., Docherty, K. E., & Weaver, J. M. (2014). Alignment verification for electron beam lithography. Microelectronic Engineering, 123, 9-12.